Verilog HDL: VLSI Hardware Design Comprehensive Masterclass - Udemy, The Complete Python Bootcamp From Zero to Hero in Python - Udemy, HDLBits — Verilog Practice.
Tel Aviv University
2020 - 2024
Academic projects include Tomasulo project (Computer Architecture) - C, High&Low Level SP (Advanced Lab In Computer Architecture) - C, Assembly and Verilog, ALU 4 bit (Introduction to VLSI Design) - Virtuoso, SIMP Processor Simulator (Computer Organization) - C & Assembly, Client-Server System with scheduling, framing and multiplexing (Introduction to Computer Communications) - C, Bitcoin RTL-to-GDSII (Digital VLSI Design) - FC, SystemVerilog and Euclide, Autonomous robot line following and obst
Hakfar Hayarok
2009 - 2015
“MOFET” Class Majored in Physics & Computer-Science.