Experienced FPGA Engineer with 4 years of practical experience in designing and debugging RTL codes for various Email protocols. Skilled in SystemVerilog HDL and Verilog HDL with a strong background in using Xilinx and Altera Phone development kits. Achieved rapid prototyping of multiple high-speed packet modules, strong problem-solving skills and ensuring robust performance in a demanding environment. Looking for jobs that will challenge me and make me a better engineer.